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Connectorless Debugging Port Landing Pads (J34)
UCF Location Constraints
Figure 15-11 provides the User Constraint File (UCF) constraints for the accessory headers,
including the I/O pin assignment and the I/O standard used.
# ==== 6-pin header J18 ====
NET "J18_IO<1>"
NET "J18_IO<2>"
NET "J18_IO<3>"
NET "J18_IO<4>"
LOC = "AA21"
LOC = "AB21"
LOC = "AA19"
LOC = "AB19"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
SLEW
SLEW
SLEW
SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
# ==== 6-pin header J19 ====
# These four connections go to
through-hole
pads, not to a connector.
NET "J19_IO<1>"
NET "J19_IO<2>"
NET "J19_IO<3>"
NET "J19_IO<4>"
LOC = "Y18" |
LOC = "W18" |
LOC = "V17" |
LOC = "W17" |
IOSTANDARD =
IOSTANDARD =
IOSTANDARD =
IOSTANDARD =
LVCMOS33 | SLEW = SLOW |
LVCMOS33 | SLEW = SLOW |
LVCMOS33 | SLEW = SLOW |
LVCMOS33 | SLEW = SLOW |
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
# ==== 6-pin header J20 ====
NET "J20_IO<1>"
NET "J20_IO<2>"
NET "J20_IO<3>"
NET "J20_IO<4>"
LOC = "V14"
LOC = "V15"
LOC = "W16"
LOC = "V16"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
SLEW
SLEW
SLEW
SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
Figure 15-11:
UCF Location Constraints for Six-Pin Accessory Headers
Connectorless Debugging Port Landing Pads (J34)
Landing pads for a connectorless debugging port are provided as the J34 header. There is
no physical connector on the board. Instead a connectorless probe, such as those available
from Agilent, provides an interface to a logic analyzer. This debugging port is intended
primarily for the Xilinx ChipScope Pro software with the Agilent FPGA Dynamic Probe. It
can, however, be used with either the Agilent or Tektronix probes, without the ChipScope
software, using FPGA Editor ’s probe command.
?
?
?
?
Xilinx ChipScope Pro Tool
www.xilinx.com/ise/optional_prod/cspro.htm
Agilent B4655A FPGA Dynamic Probe for Logic Analyzer
www.home.agilent.com/agilent/redirector.jspx?action=ref&cname=PRODUCT
&ckey=351182&lc=eng&cc=US
Agilent 5404A/6A Pro Series Soft Touch Connector
http://www.home.agilent.com/agilent/product.jspx?cc=US&lc=eng
&pageMode=OV&pid=430362&ct=PRODUCT&id=430362
Tektronix P69xx Probe Modules with D-Max Technology
www.tek.com/products/accessories/logic_analyzers/p6800_p6900.html
Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com
UG334 (v1.1) June 19, 2008
131
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